(a) Field of the Invention
The present invention relates to a physical hierarchical technology for software-defined radio systems. More specifically, the present invention relates to a digital filter for software-defined radio systems, a digital intermediate frequency signal processing apparatus having the digital filter, and a method thereof that supports multiple communication standards.
(b) Description of the Related Art
With the advance of integrated circuit (IC) technology, the performance of digital signal processing has been enhanced with a reduced cost, while expanding digital signal processing areas in the design of modems as well as digital communication/processing areas in a communication system.
Among the digital communication/processing areas, digital transmitter/receiver filters effectively restrain the band of signals, form signal waveforms, and prevent inter-channel interference from adjacent channels to minimize inter-symbol interference, i.e., distortion caused by an overlap of signal waveforms.
The recent enhancement of IC technology has realized the digitalization of a transmitter/receiver filter, which is implemented by a method of using a Nyquist filter causing no inter-signal interference at the receiver as one stage, or a method of dividing the filter into a transmitter filter and a receiver filter and using the filters as two stages.
More specifically, in the former method, the Nyquist filter designed by Nyquist for the first time can be readily designed as a finite impulse response (FIR) filter having a linear phase. The latter method has a problem with complicated design in that calculations of the transmitter and receiver filters must be performed simultaneously, while satisfying a Nyquist condition that there must not be inter-symbol interference (ISI) to the multiplication of the frequency responses of the two filters.
The linear phase FIR filter has a symmetric time-domain impulse response to reduce a cost of implementation by half, and halves the number of coefficients to be calculated in design to reduce the required time for calculations. With a frequency-based group delay regularly given due to a characteristic of the linear phase, the linear phase FIR is advantageous in symbol synchronization in digital communication systems and relatively so in non-linear distortion. The FIR filter, if implemented by VLSI (Very Large Scale Integrated) technology, has a structure basically comprised of multipliers and summators. But the use of multipliers in high-speed application systems is not desirable in the aspect of both complexity and speed.
There is no flexibility for multipliers in ASIC (Application Specific Integrated Circuit) of digital filters for a specific application. So, the filter coefficient is desirably designed to have a discrete coefficient representation for the sake of a simpler coefficient implementation.
The filter coefficient having a discrete coefficient representation, particularly comprised of a summation of power-of-2 (½N) coefficients, is simply implemented with summations and shifts, reducing a cost of hardware and avoiding a frequency response distortion caused by coefficient quantization.
On the other hand, an efficient VLSL implementation can also be achieved for the transmitter/receiver filter divided into transmitter and receiver by using a discrete coefficient. Generally, the linearity gives an optimal solution of the problem in the design of a filter having a discrete coefficient. But this develops to a problem of non-linear optimization that must be solved using various combination-optimizing algorithms for a problem having a discrete solution.
The basic concept of the software-defined radio (hereinafter referred to as “SDR”) system using the digital filters implies a radio system that drives all the functions of the communication system other than antennas completely in software to reconstruct all the communication functions. It is the object of the system of this category to introduce an open structure concept such as a computer to make the respective components of the transceiver into modules and define the interface between the modules in software, thereby implementing multi-standard communication equipment simply by replacement of software for the respective communication standards.
Digitalization is performed at a position nearest to the antenna, and all the protocol stacks including a physical layer are defined in software to enable a multi-band/multi-mode communication system. The basic hardware necessary for the implementation includes a wideband analog RF (Radio Frequency) front-end and a general digital processor reconfigurable with a high processing speed. For IF (Intermediate Frequency) processing of a digitalized signal, a digital down-converter is used at the RF end to convert the digital signal to a baseband signal. A receiver filter is a very important part of the digital down-converter, and must be reconfigurable for the respective communication standards according to the basic concept of SDR.
The SDR system of this characteristic, which is based on a terminal for supporting multiple communication standards, must include all resources for supporting the respective standards.
It is, however, undesirable to include all hardware for the respective standards in the aspect of high cost and complexity. To solve this problem, digital signal processing (DSP) is of great importance in the SDR system. The introduction of DSP leads to improved flexibility and performance of the SDR system, relative to the existing analog technology. Namely, a digital intermediate frequency signal processor is necessary because reconfiguration must be guaranteed for RF, IF, and baseband in order to implement the physical layer of the SDR system.
A technology related to the digital intermediate frequency signal processing is disclosed in Korean Patent No. 10-1999-26632 patented by Hyundai Electronics Industries Co., Ltd. under the title of “Intermediate frequency sharing dual mode mobile terminal”, which defines frequencies to share frequency mixers and share a band-pass filter and an intermediate frequency processor, thereby implementing an analog intermediate frequency processor in a small size.